(1) Field of the Invention
The present invention relates to the manufacture of very large (VLSI) and ultra large scale integrated (ULSI) circuits, and more particularly to a tilt-angle implant method of forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories, as well as to an optimum implant angle method of forming DDDs (Doubly Doped Drains) in flash memory applications.
(2) Description of the Related Art
As the device dimensions in very large (VLSI) and ultra large scale integrated (ULSI) circuits are reduced and the supply voltage remains constant, the lateral electric filed generated in MOS (Metal-Oxide-Semiconductor) devices increases. The maximum electric field, E.sub.M, in a MOSFET (Field Effect Transistor) occurs near the drain during saturated operation. As is known in the art, E.sub.M increases as device dimensions shrink including the length of the channel, L.sub.eff, as well as due to the thinner gate oxides and shallower junctions. If the electric field becomes strong enough, it can give rise to the so-called hot-carrier effects in MOS FETs (Field-Effect Transistor) devices. If the carriers are electrons such as in n-channel NMOS FETs rather than holes such as in p-channel PMOS FETs, the effects of hot-electrons become even more severe than hot-hole effects because of the higher electron mobility.
Electrons in high electric fields become "hot" electrons because they gain kinetic energy. Such hot electrons--which become hot near the drain edge of the channels because that is where the high electric filed exists--can cause several effects in the device. First, electrons that acquire high energy of more than 1.5 KeV can lose it through, what is known as, impact ionization, which generates electron-hole pairs. The total number of electron-hole pairs generated by impact ionization is exponentially dependent on the reciprocal of the electric field. In some cases, this electron-hole pair generation can lead to a form of avalanche breakdown, as is also known in the art. Second, the hot holes and electrons can overcome the potential energy barrier between the silicon and the SiO.sub.2, thereby causing hot carriers to become injected into the gate oxide. This in turn leads to long-term device degradation and reduced reliability. It is disclosed in this invention a method of reducing the high electric field at the drain region of a MOSFET through a more gradual, or graded, change in the doping concentration at the drain/channel interface implemented by using ion implantation at certain tilt-angles which can provide optimum conditions for well-behaving junctions.
In prior art, different methods have been proposed to provide the graded semiconductor substrate junction for control of the hot-carrier-effect (HCE) within MOSFET devices. These include: (1) the Lightly Doped Drain (LDD) method whereby two partially overlapping ion implants at substantially different ion implant doses are provided into a semiconductor substrate to yield a lightly doped semiconductor substrate region beneath the gate electrode edges and a heavily doped semiconductor substrate region forming the remote source/drain electrodes, and (2) the Doubly Doped Drain (DDD) method whereby two different dopant ions of substantially different diffusivity are implanted into the same region of the semiconductor substrate and thermally annealed to provide the graded junction which includes the highly doped source/drain electrodes and the lightly doped semiconductor substrate region beneath the gate electrode edges. These prior art methods are shown in FIGS. 1a and 1b as follows, where substrate (100) has a channel region (111) adjacent to source/drain regions (113) overlapping the overlying edges of gate oxide (120) separating gate (130) from the substrate:
In FIG. 1a, substrate (100) is implanted with a heavy implant to create regions (115), and an implant with lighter doping concentration to form regions (113), thus forming an LDD. The two implants are performed using two different masks, where one of them is the gate (130) itself. A smaller electric field results at the channel (111)/ drain (113) interface than would exist in a device in which a single heavy implant were to be performed, due to a reduction in the difference in dopant concentrations between the channel and the drain regions adjacent to it.
In FIG. 1b, a DDD is formed to alleviate the double problem of drain/channel junction breakdown and hot electron injection into gate oxide (120). In this method, two implants are performed using the same mask, namely, gate itself (130) as the mask, which result in regions (117) and (119) shown in FIG. 1b. The first implant comprises phosphorous followed by a second implant comprising arsenic. The greater diffusivity of phosphorus causes it to diffuse laterally during the implant anneal, to form region (117) which has a lighter resultant dopant concentration than adjacent region (119) formed by the arsenic implant.
As described by Ko in U.S. Pat. No. 5,565,369, a disadvantage of the doubly doped drain approach is an increase in source/drain junction capacitance. This leads to an increase in the RC constant and an undesirably higher propagation delay, which results in a slower performance of the circuits formed with these devices. In order to solve these problems, along with the hot electron problem, Ko provides a silicon substrate with field isolation regions and a gate structure. A layer of photoresist is formed on the field isolation region, the silicon substrate, and the gate structure. The photoresist is patterned to expose the silicon substrate and the gate structure, but covers an area of the silicon substrate that is offset from the field isolation regions. A first ion implant is performed in a vertical direction in exposed regions of the silicon substrate, with suitable dopant having a high doping concentration. The photoresist is removed. A second ion implant is performed in a vertical direction in the silicon substrate, with suitable dopant with higher doping concentration than the first ion implant, in regions between the field isolation regions and the gate structure. The substrate is heated to drive in both the dopants to form the DDD structure.
Similarly, Gardner, et al., of U.S. Pat. No. 5,793,090 show an integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is one which has relatively high drive strength, low contact resistivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.
Urayama, on the other hand, proposes in U.S. Pat. No. 5,851,869, the use of a DDD structure in the manufacture of a semiconductor device having low contact resistance. His device is capable of stably operating even at a low voltage through having in a substrate an oozed diffusion region, a low resistivity region, and a DDD structure transistor formed on another region of the surface of the substrate, wherein a length of a portion of the low resistivity region overlapping a conductive film is substantially the same as a length of a portion of the deep source and drain regions of the DDD structure overlapping the gate electrode. Mei of U.S. Pat. No. 5,498,554 also shows a method of making an integrated circuit containing low voltage PMOS and/or NMOS devices as well as high voltage PMOS and/or NMOS devices. Low and high values are obtained by selecting impurity concentration levels appropriate for different regions in a substrate.
Lee of U.S. Pat. No. 5,770,502 discloses a method of forming a modified DDD junction structure which is formed on stack gate structure side on which a floating gate and a control gate are laminated and a non-DDD structure is formed on split gate side, by forming a first impurity region through a tilt-angle implanting of impurity ions at a high level of energy and the forming a second impurity region through a tilt-angle implanting of impurity ions at a lower level of energy using a spacer.
Pan, in U.S. Pat. No. 5,750,435, teaches a method for minimizing the hot carrier effect in N-MOSFET devices by implanting into the gate oxide regions beneath the gate electrode edges a dose of a hardening ion. The hardening ion is either nitrogen ion or fluorine ion. The hardening ion is implanted at an angle non-orthogonal to the plane of the semiconductor substrate through means of a large tilt-angle ion implant process.
It is disclosed later in the embodiments of the present invention a different method of forming LDDs and DDDs in flash memory applications through an optimal implant angle. This method provides a good doping concentration contour and profile with the attendant advantage of having improved junction breakdown characteristics. Other advantages include the increased program speed, reduced program current, increased read current and reduced drain disturb of the flash memory cell.